The inventive concept disclosed herein relates to a frequency multiplier and a method of multiplying a frequency.
A delay locked loop (DLL) may be used to generate an internal clock in an electronic device. A conventional delay locked loop delays a received external clock by a predetermined time using a delay line to generate an internal clock synchronized with the external clock. As compared with a clock generating device based on a phase locked loop and a local oscillator, a clock generating device based on the delay locked loop no jitter accumulation and a simple loop filter structure, thus it has a small phase noise and can be miniaturized. In case of a semiconductor memory device, a data transmission speed can be increased by using an internal clock which is formed by frequency multiplication of the external clock and an error can be reduced when transmitting data at high speed by using clocks having an accurate phase delay and an accurate duty rate.
A frequency multiplier using a delay locked loop may include a pulse generator, an edge combiner and a multiplication rate control unit. The pulse generator receives a delayed signal from a delay locked loop to generate a pulse using for example a flip-flop circuit. An overlap due to a variation of process voltage temperature (PVT) may occur between pulses generated by the pulse generator. The overlap leads to an increase of power consumption of the edge combiner, thereby increasing a power consumption of the frequency multiplier.
The edge combiner generates a clock signal using a PMOS or NMOS transistor. In this case, as a multiplication rate becomes high, the number of PMOSs and NMOSs that are necessary is increased, thereby increasing junction capacitance of output terminal. As a result, as a multiplication rate increases, the maximum frequency that can be generated is reduced and power consumption of frequency multiplier increases.